Hiromichi Yamada
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
1995–2007
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2007 | DSN | A Cost-Effective Dependable Microcontroller Architecture with Instruction-Level Rollback for Soft Error Recovery. | Teruaki Sakata, Teppei Hirotsu, Hiromichi Yamada, Takeshi Kataoka |
| 1997 | VTS | A practical approach to instruction-based test generation for functional modules of VLSI processors. | Kazumi Hatayama, Kazunori Hikone, Takeshi Miyazaki, Hiromichi Yamada |
| 1995 | ICCD | A 13.3ns double-precision floating-point ALU and multiplier. | Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto |