Hironori Nakajo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
24
Venues
10
Active years
1996–2011
Best venue rank
National
Where they publish
Papers
24 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | SC | A memory accelerator with gather functions for bandwidth-bound irregular applications. | Noboru Tanabe, Boonyasitpichai Nuttapon, Hironori Nakajo, Yuka Ogawa, Junko Kogou, Masami Takata, Kazuki Joe |
| 2011 | RTCSA | Feature Selection and Activity Recognition to Detect Water Waste from Water Tap Usage. | Trang Thuy Vu, Akifumi Sokan, Hironori Nakajo, Kaori Fujinami, Jaakko Suutala, Pekka Siirtola, Tuomo Alasalmi, Ari Pitknen, Juha Rning |
| 2009 | DSD | An Effective Replacement Strategy of Cache Memory for an SMT Processor. | Yoshiyasu Ogasawara, Hironori Nakajo |
| 2009 | ICPADS | Network Interface Architecture for Scalable Message Queue Processing. | Noboru Tanabe, Atsushi Ohta, Pulung Waskito, Hironori Nakajo |
| 2009 | PDPTA | The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. | Noboru Tanabe, Manami Sasaki, Hironori Nakajo, Masami Takata, Kazuki Joe |
| 2008 | PDCAT | An Enhancer of Memory and Network for Cluster and its Applications. | Noboru Tanabe, Hironori Nakajo |
| 2007 | PDPTA | Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. | Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo |
| 2007 | PDPTA | Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. | Satoshi Watanabe, Yoshiyasu Ogasawara, Ippei Tate, Hirofumi Yano, Hironori Nakajo |
| 2006 | FPL | DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. | Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe |
| 2006 | PDPTA | Implementation of PC Cluster System with Memory Mapped File by Commodity OS. | Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki |
| 2006 | PDPTA | Towards Reconfigurable Cache Memory for a Multithreaded Processor. | Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo |
| 2006 | PDPTA | A Model of Implementable SMT Processor on FPGA. | Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo |
| 2005 | PDCAT | Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. | Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo |
| 2005 | PDPTA | A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. | Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo |
| 2005 | PDPTA | A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. | Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |
| 2005 | PDPTA | Development of a Thread Scheduler for SMT Processor Architecture. | Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki |
| 2004 | PDPTA | Dynamic Allocation of Physical Register Banks for an SMT Processor. | Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo |
| 2003 | PDPTA | Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. | Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki |
| 2003 | PDPTA | Implementation and Evaluation of a Thread Library for Multithreaded Architecture. | Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki |
| 2003 | PDPTA | A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. | Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki |
| 2000 | CLUSTER | MEMOnet : Network interface plugged into a memory slot. | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano |
| 2000 | PDPTA | Coherence Protocol for Home Proxy Cache on RHiNET. | Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano |
| 1997 | ICS | An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. | Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda |
| 1996 | ICDCS | A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. | Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda |