| 2018 | ISCAS | Image-Classifier Deep Convolutional Neural Network Training by 9-bit Dedicated Hardware to Realize Validation Accuracy and Energy Efficiency Superior to the Half Precision Floating Point Format. | Shin-ichi O'Uchi, Hiroshi Fuketa, Tsutomu Ikegami, Wakana Nogami, Takashi Matsukawa, Tomohiro Kudoh, Ryousei Takano |
| 2011 | DAC | A closed-form expression for estimating minimum operating voltage (V | Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
| 2011 | ISLPED | 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V | Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai |
| 2011 | ISLPED | Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. | Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai |
| 2010 | ASPDAC | Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2009 | ASPDAC | Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |
| 2008 | ISLPED | Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits. | Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye |