Hisakazu Edamatsu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
1987–1998
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | ASPDAC | Pre-layout Delay Calculation Specification for CMOS ASIC Libraries. | Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi |
| 1996 | DAC | Design Methodologies for consumer-use video signal processing LSIs. | Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa |
| 1987 | ARITH | Design of high speed MOS multiplier and divider using redundant binary representation. | Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi |