Design of high speed MOS multiplier and divider using redundant binary representation.
Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi
VenueCARITH
Year1987
ProceedingsIEEE Symposium on Computer Arithmetic
DBLP recordconf/arith/KuninobuNETT87 ↗
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