Skip to content

Holger Eisenreich

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

6

Venues

3

Active years

2010–2019

Best venue rank

A*

Where they publish

Papers

6 indexed papers, newest first.

YearVenueTitleAuthors
2019ISCASA Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.Florian Schraut, Holger Eisenreich, Sebastian Hppner, Christian Mayr
2017DACA Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.Sebastian Haas, Tobias Seifert, Benedikt Nthen, Stefan Scholze, Sebastian Hppner, Andreas Dixius, Esther Prez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Mats, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederstrm, Dennis Walter, Stephan Henker, Stefan Hnzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, Ren Schffny, Christian Mayr, Gerhard P. Fettweis
2016DACAn MPSoC for energy-efficient database query processing.Sebastian Haas, Oliver Arnold, Benedikt Nthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Hppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jrg Schreiter, Holger Eisenreich, Jens-Uwe Schller, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Mats, Christian Mayr, Ren Schffny, Gerhard P. Fettweis
2014ISCASA compact on-chip IR-drop measurement system in 28 nm CMOS technology.Sebastian Dietel, Sebastian Hppner, Holger Eisenreich, Georg Ellguth, Stefan Hnzsche, Stephan Henker, Ren Schffny, Tim Brauninger, Ulrich Fiedler
2012ISCASA power management architecture for fast per-core DVFS in heterogeneous MPSoCs.Sebastian Hppner, Chenming Shao, Holger Eisenreich, Georg Ellguth, Mario Ander, Ren Schffny
2010DATELow power design of the X-GOLDWolfgang Raab, Jrg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth