Hong-Ting Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2011–2011
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ASPDAC | An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs. | Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho |
| 2011 | ICCAD | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. | Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu |
| 2011 | ISLPED | Pulsed-latch-based clock tree migration for dynamic power reduction. | Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho |