Hsiang-Yun Cheng
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
29
Venues
12
Active years
2010–2026
Best venue rank
A*
Where they publish
Papers
29 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISLPED | Tris-GCN: A 3D NAND Flash-based In-Storage Processing Architecture for GCN Acceleration. | Yi-Wa Wu, Jia-You Li, Chi-Jung Chen, Ching (Ryan) Cheng, Chia-Chun Wang, Chin-Fu Nien, Hsiang-Yun Cheng |
| 2025 | ASPDAC | Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. | Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu |
| 2025 | ASPDAC | ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. | Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng |
| 2025 | ASPDAC | In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. | You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li |
| 2025 | DAC | Segmented Angular Pre-Processing for Accurate and Efficient In-Memory Vector Similarity Search. | Chi-Tse Huang, Jen-Chieh Wang, Hsiang-Yun Cheng, An-Yeu Andy Wu |
| 2025 | DAC | Energy-Efficient Large-Scale Vector Similarity Search in NAND-Flash via Hybrid Matching. | Chih-Yu Hu, Chi-Tse Huang, Hao-Wei Chiang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu |
| 2025 | DATE | Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. | Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang |
| 2024 | DATE | BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. | Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu |
| 2024 | DATE | ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. | Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng |
| 2024 | ISCA | ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems. | Hao-Wei Chiang, Chin-Fu Nien, Hsiang-Yun Cheng, Kuei-Po Huang |
| 2023 | CASES | Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. | Jrg Henkel, Lokesh Siddhu, Lars Bauer, Jrgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jernimo Castrilln, Asif Ali Khan, Hamid Farzaneh, Joo Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng |
| 2023 | HPCA | Tensor Movement Orchestration in Multi-GPU Training Systems. | Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang |
| 2022 | ASPDAC | This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. | Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai |
| 2022 | DATE | RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment. | Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng |
| 2022 | HPCA | Efficient Bad Block Management with Cluster Similarity. | Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo |
| 2021 | DAC | RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. | Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng |
| 2021 | DATE | Future Computing Platform Design: A Cross-Layer Design Approach. | Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo |
| 2021 | ICCD | ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. | Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng |
| 2021 | ISPASS | Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. | Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang |
| 2020 | DATE | GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. | Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, Che-Ching Lin |
| 2019 | ICCAD | The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. | Jrg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang |
| 2019 | ISCA | Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. | Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li |
| 2018 | ICCAD | DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. | Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang |
| 2017 | ISPASS | Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. | Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung |
| 2016 | ISCA | LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. | Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie |
| 2016 | ISCAS | Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. | Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin |
| 2015 | DAC | Core vs. uncore: the heart of darkness. | Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin |
| 2014 | ISLPED | EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. | Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie |
| 2010 | MICRO | Memory Latency Reduction via Thread Throttling. | Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang |