| 2022 | ICASSP | A Clustering-based ML Scheme for Capacity Approaching Soft Level Sensing in 3D TLC NAND. | Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang |
| 2021 | ISCAS | A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. | Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang |
| 2020 | DATE | Embedding Hierarchical Signal to Siamese Network for Fast Name Rectification. | Yi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang |
| 2020 | ISCAS | An Area-Efficient High-Throughput SM4 Accelerator with SCA-Countermeasure for TV Applications. | Wei Chiang, Hsie-Chia Chang, Chen-Yi Lee |
| 2018 | ISCAS | A 188-Length Full Code Rate 333Mbps 1.08mm | Po-Hsun Chang, Chen-Yang Lin, Chia-Hsiang Sun, Yen-Chin Liao, Hsie-Chia Chang |
| 2018 | ITW | Generalized Globally-Coupled Low-Density Parity-Check Codes. | Yen-Chin Liao, Hsie-Chia Chang, Shu Lin |
| 2015 | ISCAS | A 3.46 Gb/s (9141, 8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications. | Kin-Chu Ho, Chih-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang, Chen-Yi Lee |
| 2014 | ISCAS | Area-efficient TFM-based stochastic decoder design for non-binary LDPC codes. | Chih-Wen Yang, Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee |
| 2012 | CHES | An Efficient Countermeasure against Correlation Power-Analysis Attacks with Randomized Montgomery Operations for DF-ECC Processor. | Jen-Wei Lee, Szu-Chi Chung, Hsie-Chia Chang, Chen-Yi Lee |
| 2012 | ICASSP | A fully parallel BCH codec with double error correcting capability for NOR flash applications. | Chia-Ching Chu, Yi-Min Lin, Chi-Heng Yang, Hsie-Chia Chang |
| 2012 | ISCAS | A high-performance elliptic curve cryptographic processor over GF(p) with SPA resistance. | Szu-Chi Chung, Jen-Wei Lee, Hsie-Chia Chang, Chen-Yi Lee |
| 2012 | ISCAS | Stochastic decoding for LDPC convolutional codes. | Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee |
| 2012 | ISITA | An improved LT encoding scheme with extended chain lengths. | Kuo-Kuang Yen, Chih-Lung Chen, Hsie-Chia Chang |
| 2011 | ISCAS | A dual-field elliptic curve cryptographic processor with a radix-4 unified division unit. | Yao-Lin Chen, Jen-Wei Lee, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee |
| 2010 | ISCAS | An improved soft BCH decoder with one extra error compensation. | Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee |
| 2010 | ISCAS | A multiple code-rate turbo decoder based on reciprocal dual trellis architecture. | Chen-Yang Lin, Cheng-Chi Wong, Hsie-Chia Chang |
| 2008 | ISCAS | Structured LDPCcodes with low error floor based on PEG tanner graphs. | Yi-Kai Lin, Chin-Lung Chen, Yen-Chin Liao, Hsie-Chia Chang |
| 2008 | ISCAS | Multi-mode message passing switch networks applied for QC-LDPC decoder. | Chih-Hao Liu, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yarsun Hsua |
| 2006 | ISCAS | A self-compensation fixed-width booth multiplier and its 128-point FFT applications. | Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang |
| 2004 | ISCAS | Multi-level memory systems using error control codes. | Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang |
| 2004 | ISCAS | A power and area efficient multi-mode FEC processor. | Yi-Chen Tseng, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee |
| 2001 | ISCAS | An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. | Hsie-Chia Chang, Chen-Yi Lee |