Hsinwei Chou
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2005–2015
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ICCAD | Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. | Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin |
| 2005 | ASPDAC | Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation. | Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen |