| 2022 | APWEB | Cross-platform Product Matching Based on Knowledge Graph. | Wenlong Liu, Jiahua Pan, Xingyu Zhang, Xinxin Gong, Yang Ye, Xujin Zhao, Xin Wang, Kent Wu, Hua Xiang, Qingpeng Zhang |
| 2022 | ICCAD | A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. | Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam |
| 2021 | ICCAD | FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer. | Rongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam |
| 2020 | DATE | Self-Aligned Double-Patterning Aware Legalization. | Hua Xiang, Gi-Joon Nam, Gustavo E. Tllez, Shyam Ramji, Xiaoqing Xu |
| 2020 | ICCAD | Routing-Free Crosstalk Prediction. | Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam |
| 2014 | DAC | Row Based Dual-VDD Island Generation and Placement. | Hua Xiang, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu |
| 2013 | ICCAD | LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs. | Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri |
| 2013 | ICCAD | Depth controlled symmetric function fanin tree restructure. | Hua Xiang, Lakshmi N. Reddy, Louise Trevillyan, Ruchir Puri |
| 2010 | DAC | History-based VLSI legalization using network flow. | Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri |
| 2008 | SC | Communication avoiding Gaussian elimination. | Laura Grigori, James Demmel, Hua Xiang |
| 2007 | ASPDAC | Coupling-aware Dummy Metal Insertion for Lithography. | Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang |
| 2007 | DAC | TROY: Track Router with Yield-driven Wire Planning. | Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan |
| 2006 | ICCAD | Wire density driven global routing for CMP variation and timing. | Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri |
| 2005 | EUC | An Advanced Mental State Transition Network and Psychological Experiments. | Peilin Jiang, Hua Xiang, Fuji Ren, Shingo Kuroiwa |
| 2003 | FPGA | Wire type assignment for FPGA routing. | Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun |
| 2003 | ICCAD | Bus-Driven Floorplanning. | Hua Xiang, Xiaoping Tang, Martin D. F. Wong |
| 2002 | DAC | An algorithm for integrated pin assignment and buffer planning. | Hua Xiang, D. F. Wong, Xiaoping Tang |
| 2002 | DATE | A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. | Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu |
| 2002 | ICCAD | ECO algorithms for removing overlaps between power rails and signal wires. | Hua Xiang, Kai-Yuan Chao, D. F. Wong |
| 2001 | ICCAD | A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. | Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong |
| 2001 | ICCAD | An Algorithm for Simultaneous Pin Assignment and Routing. | Hua Xiang, Xiaoping Tang, D. F. Wong |