Huamin Cao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2012–2012
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | DDECS | A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique. | Xiang Zheng, Ming Liu, Hong Chen, Huamin Cao, Cong Wang, Zhiqiang Gao |