| 2026 | DATE | Optimizing Multibit Flip-Flop Banking via Agile In-Placement PPA Co-Optimization. | Huan-Yuan Chen, Yu-Ruei Lin, Mark Po-Hung Lin, Hung-Ming Chen |
| 2025 | ASPDAC | On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis. | Hao-Ju Chang, Yu-Hung Chen, Hao-Wei Huang, Yihua Yeh, Hung-Ming Chen, Chien-Nan Jimmy Liu |
| 2025 | ASPDAC | Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization. | Cheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-Hua Wang, Yao-Wen Chang, Hung-Ming Chen |
| 2025 | DAC | Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze Routing. | Cheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Yang Hsu, Yao-Wen Chang, Hung-Ming Chen |
| 2025 | DATE | Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis. | Siou-Sian Lin, Shih-Yu Chen, Yu-Ping Huang, Tzu-Chuan Lin, Hung-Ming Chen, Wei-Zen Chen |
| 2025 | ISCAS | Irregular Operation-Unit-based Compression for Non-Volatile Computation-in-Memory Accelerator. | Liang-Te Huang, Wei Lu, Hung-Ming Chen, Po-Tsang Huang |
| 2024 | ICCAD | CFIRSTNET: Comprehensive Features for Static IR Drop Estimation with Neural Network. | Yu-Tung Liu, Yu-Hao Cheng, Shao-Yu Wu, Hung-Ming Chen |
| 2024 | ISCAS | A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. | Wei Lu, Han-Hsiang Pei, Jheng-Rong Yu, Hung-Ming Chen, Po-Tsang Huang |
| 2023 | ASPDAC | On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. | Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2023 | ASPDAC | DPRoute: Deep Learning Framework for Package Routing. | Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen |
| 2022 | DATE | Practical Substrate Design Considering Symmetrical and Shielding Routes. | Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho |
| 2022 | DATE | DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. | Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou |
| 2020 | DAC | Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. | Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin |
| 2020 | DATE | On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages. | Jyun-Ru Jiang, Yun-Chih Kuo, Simon Yi-Hung Chen, Hung-Ming Chen |
| 2020 | ICCAD | On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. | Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Kster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou |
| 2020 | ICCAD | Achieving Analog Layout Integrity through Learning and Migration Invited Talk. | Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2019 | DAC | An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. | Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen |
| 2019 | ICCAD | Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. | Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2019 | ISCAS | More Effective Power Network Prototyping by Analytical and Centroid Learning. | Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen |
| 2018 | ASPDAC | Performance-preserved analog routing methodology via wire load reduction. | Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2018 | ASPDAC | Multi-level droplet routing in active-matrix based digital-microfluidic biochips. | Guan-Ruei Lu, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen |
| 2018 | DAC | Analog placement with current flow and symmetry constraints using PCP-SP. | Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu |
| 2018 | ICCAD | Extending ML-OARSMT to net open locator with efficient and effective boolean operations. | Bing-Hui Jiang, Hung-Ming Chen |
| 2017 | ASPDAC | Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. | Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou |
| 2017 | ASPDAC | On reliability hardening in cyber-physical digital-microfluidic biochips. | Guan-Ruei Lu, Guan-Ming Huang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen |
| 2015 | ASPDAC | An approach to anchoring and placing high performance custom digital designs. | Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen |
| 2014 | ASPDAC | Routability-driven bump assignment for chip-package co-design. | Meng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen |
| 2014 | DATE | Cost-effective decap selection for beyond die power integrity. | Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen |
| 2014 | DATE | Memcomputing: The cape of good hope: [Extended special session description]. | Yiyu Shi, Hung-Ming Chen |
| 2014 | ICCAD | Planning and placing power clamps for effective CDM protection. | Hsin-Chun Lin, Shih-Ying Sean Liu, Hung-Ming Chen |
| 2014 | ICCD | Improving power delivery network design by practical methodologies. | Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai |
| 2013 | DATE | A network-flow based algorithm for power density mitigation at post-placement stage. | Shih-Ying Sean Liu, Ren-Guo Luo, Hung-Ming Chen |
| 2013 | DATE | Effective power network prototyping via statistical-based clustering and sequential linear programming. | Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee |
| 2013 | DATE | PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. | Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin |
| 2013 | ICCAD | Efficient analog layout prototyping by layout reuse with routing preservation. | Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin |
| 2012 | ASPDAC | A fast thermal aware placement with accurate thermal analysis based on Green function. | Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen |
| 2012 | DATE | On effective flip-chip routing via pseudo single redistribution layer. | Hsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen |
| 2012 | DATE | Agglomerative-based flip-flop merging with signal wirelength optimization. | Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen |
| 2012 | ICCAD | Configurable analog routing methodology via technology and design constraint unification. | Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu |
| 2011 | ASPDAC | Row-based area-array I/O design planning in concurrent chip-package design flow. | Ren-Jie Lee, Hung-Ming Chen |
| 2011 | DATE | On routing fixed escaped boundary pins for high speed boards. | Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani |
| 2011 | ICCAD | Fast analog layout prototyping for nanometer design migration. | Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen |
| 2010 | ASPDAC | Technology mapping with crosstalk noise avoidance. | Fang-Yu Fan, Hung-Ming Chen, I-Min Liu |
| 2009 | DATE | Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. | Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih |
| 2007 | ASPDAC | Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. | Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen |
| 2007 | ASPDAC | On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. | Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu |
| 2007 | ICCAD | A selective pattern-compression scheme for power and test-data reduction. | Chia-Yi Lin, Hung-Ming Chen |
| 2006 | PAKDD | Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier. | Shinn-Ying Ho, Chih-Hung Hsieh, Kuan-Wei Chen, Hui-Ling Huang, Hung-Ming Chen, Shinn-Jang Ho |
| 2005 | CEC | Efficient gene selection for classification of microarray data. | Shinn-Ying Ho, Chong-Cheng Lee, Hung-Ming Chen, Hui-Ling Huang |
| 2005 | CEC | Flexible protein-ligand docking using particle swarm optimization. | Bo-Fu Liu, Hung-Ming Chen, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho |
| 2005 | GECCO | MeSwarm: memetic particle swarm optimization. | Bo-Fu Liu, Hung-Ming Chen, Jian-Hung Chen, Shiow-Fen Hwang, Shinn-Ying Ho |
| 2004 | ICCD | I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. | Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang |
| 2004 | PRICAI | Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm. | Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho |
| 2003 | ASPDAC | Floorplanning with power supply noise avoidance. | Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong |
| 2003 | DATE | Global Wire Bus Configuration with Minimum Delay Uncertainty. | Li-Da Huang, Hung-Ming Chen, D. F. Wong |
| 2001 | ASPDAC | Integrated power supply planning and floorplanning. | I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong |
| 1999 | ICCAD | Integrated floorplanning and interconnect planning. | Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani |