| 2007 | ISPA | An QoS Aware Mapping of Cores Onto NoC Architectures. | Huy Nam Nguyen, Vu-Duc Ngo, Younghwan Bae, Hanjin Cho, Hae-Wook Choi |
| 2006 | ISPA | Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. | Vu-Duc Ngo, Huy Nam Nguyen, Younghwan Bae, Hanjin Cho, Hae-Wook Choi |
| 2006 | ISPA | The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. | Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi |
| 2005 | EUC | Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. | Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi |
| 1996 | RSP | Design Verification based on Hardware Emulation. | Huy Nam Nguyen, Michel Thill |
| 1995 | ASPDAC | Auriga2: a 4.7 million-transistor CISC microprocessor. | J. P. Tual, Michel Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet |
| 1995 | RSP | Application of synthesis to support hardware emulation. | Huy Nam Nguyen, Yvon Gressus, Michel D'Hoe |
| 1994 | ICCD | The Structured Logic CAD Suite Used on the DPS7000 System. | Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet |