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Hyein Lee

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

17

Venues

8

Active years

2008–2023

Best venue rank

A*

Where they publish

Papers

17 indexed papers, newest first.

YearVenueTitleAuthors
2023GLOBECOMEnergy-Efficient Downlink Semantic Generative Communication with Text-to-Image Generators.Hyein Lee, Jihong Park, Sooyoung Kim, Jinho Choi
2022APCCEvaluation of physical-layer security schemes for space-time block coding under imperfect channel estimation.Seunggyu Hwang, Hyein Lee, Sooyoung Kim
2022APCCEvaluation of Resource Allocation Methods for Integrated Satellite-Terrestrial Systems.Hyein Lee, Sooyoung Kim, Dae-Sub Oh
2020UISTSchemaBoard: Supporting Correct Assembly of Schematic Circuits using Dynamic In-Situ Visualization.Yoonji Kim, Hyein Lee, Ramkrishna Prasad, Seungwoo Je, Youngkyung Choi, Daniel Ashbrook, Ian Oakley, Andrea Bianchi
2020SiggraphAMAScreen: Augmenting Speech with Visual Cues of Lip Motions, Facial Expressions, and Text Using a Wearable Display.Hyein Lee, Yoonji Kim, Andrea Bianchi
2019CHIVirtualComponent: A Mixed-Reality Tool for Designing and Tuning Breadboarded Circuits.Yoonji Kim, Youngkyung Choi, Hyein Lee, Geehyuk Lee, Andrea Bianchi
2018CHIHapCube: A Wearable Tactile Device to Provide Tangential and Normal Pseudo-Force Feedback on a Fingertip.Hwan Kim, Hyeon-Beom Yi, Hyein Lee, Woohun Lee
2018CHIHapCube: A Fingertip-Sized Tactile Device Providing 2+1 Dimensional Pseudo-Force Feedback.Hwan Kim, Hyeon-Beom Yi, Hyein Lee, Woohun Lee
2017DACVertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang
2017ICCADOptimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu
2016ICCADMeasuring progress and value of IC implementation technology.Andrew B. Kahng, Hyein Lee, Jiajia Li
2015DACEvaluation of BEOL design rule impacts using an optimal ILP-based detailed router.Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2015ICCADScalable Detailed Placement Legalization for Complex Sub-14nm Constraints.Kwangsoo Han, Andrew B. Kahng, Hyein Lee
2014NPCParallel CYK Membership Test on GPUs.Kyoung-Hwan Kim, Sang-Min Choi, Hyein Lee, Ka Lok Man, Yo-Sub Han
2013DACSmart non-default routing for clock power reduction.Andrew B. Kahng, Seokhyeong Kang, Hyein Lee
2013ICCADHigh-performance gate sizing with a signoff timer.Andrew B. Kahng, Seokhyeong Kang, Hyein Lee, Igor L. Markov, Pankit Thapar
2008ICCADPulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.Hyein Lee, Seungwhun Paik, Youngsoo Shin