| 2025 | ASPDAC | Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks. | Thai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi |
| 2021 | DAC | Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs. | Hyojin Choi, In Huh, Seungju Kim, Jeonghoon Ko, Changwook Jeong, Hyeonsik Son, Kiwon Kwon, Joonwan Chai, Younsik Park, Jaehoon Jeong, Daesin Kim, Jung Yun Choi |
| 2012 | ASPLOS | Reducing off-chip memory traffic by selective cache management scheme in GPGPUs. | Hyojin Choi, Jae-Woo Ahn, Wonyong Sung |
| 2012 | ISCAS | Performance analysis of multi-bank DRAM with increased clock frequency. | Su-Jin Cho, Jae-Woo Ahn, Hyojin Choi, Wonyong Sung |
| 2012 | ISCAS | A simulation-based study for DRAM power reduction strategies in GPGPUs. | Hyojin Choi, Kyuyeon Hwang, Jae-Woo Ahn, Wonyong Sung |
| 2011 | ISPASS | Memory access pattern-aware DRAM performance model for multi-core systems. | Hyojin Choi, Jongbok Lee, Wonyong Sung |
| 2007 | ISCAS | Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding. | Hyojin Choi, Wonchul Lee, Wonyong Sung |