| 2025 | DATE | SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators. | Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha |
| 2025 | ICCD | Scaling Up the Sustainability of Photonic Tensor Cores With Device-Circuit-Signaling Co-Design. | Ishan G. Thakkar, Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Oluwaseun Adewunmi Alo |
| 2021 | VLSID | Silicon Photonic Microring Based Chip-Scale Accelerator for Delayed Feedback Reservoir Computing. | Sairam Sri Vatsavai, Ishan G. Thakkar |
| 2021 | SENSYS | Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic Unit. | Venkata Sai Praneeth Karempudi, Shreyan Datta, Ishan G. Thakkar |
| 2020 | ICCD | Improving the Latency-Area Tradeoffs for DRAM Design with Coarse-Grained Monolithic 3D (M3D) Integration. | Chao-Hsuan Huang, Ishan G. Thakkar |
| 2019 | CASES | Mitigating Write Disturbance in Phase Change Memory Architectures. | Chao-Hsuan Huang, Ishan G. Thakkar |
| 2018 | DAC | SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. | Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha |
| 2017 | VLSID | DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency. | Ishan G. Thakkar, Sudeep Pasricha |
| 2016 | DAC | PICO: mitigating heterodyne crosstalk due to process variations and intermodulation effects in photonic NoCs. | Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha |
| 2016 | VLSID | Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. | Ishan G. Thakkar, Sudeep Pasricha |
| 2015 | ICCD | A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses. | Ishan G. Thakkar, Sudeep Pasricha |
| 2014 | ICCD | 3D-Wiz: A novel high bandwidth, optically interfaced 3D DRAM architecture with reduced random access time. | Ishan G. Thakkar, Sudeep Pasricha |