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Itsuo Takanami

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

11

Venues

4

Active years

1982–2018

Best venue rank

A*

Where they publish

Papers

11 indexed papers, newest first.

YearVenueTitleAuthors
2018PRDCDegradable Restructuring of Mesh-Connected Processor Arrays with Spares on Orthogonal Sides.Itsuo Takanami, Masaru Fukushi
2018PRDCRestructuring Mesh-Connected Processor Arrays with Spares on Four Sides by Orthogonal Side Rotation.Itsuo Takanami, Masaru Fukushi
2017PRDCA Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays with Spares on Diagonal.Itsuo Takanami, Masaru Fukushi
2012PRDCA Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.Itsuo Takanami, Tadayoshi Horita
2009PDPTAAn Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.Tadayoshi Horita, Itsuo Takanami
2009PDPTANovel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.Kazuhiro Nishimura, Tadayoshi Horita, Masato Otsu, Itsuo Takanami
2002PRDCAn Extreme Value Injection Approach with Reduced Learning Time to Make MLNs Multiple-Weight-Fault Tolerant.Itsuo Takanami, Yasuhiro Oyama
2001PRDCAnalytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.Tadayoshi Horita, Itsuo Takanami
2000IJCNNA Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs.Itsuo Takanami, Masaru Sato, Yun Ping Yang
2000PDPTAA System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.Tadayoshi Horita, Itsuo Takanami
1982STOCTwo-Dimensional Alternating Turing MachinesKatsushi Inoue, Itsuo Takanami, Hiroshi Taniguchi