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J. B. Kuo

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

3

Venues

1

Active years

2002–2006

Best venue rank

C

Where they publish

Papers

3 indexed papers, newest first.

YearVenueTitleAuthors
2006ISCASGate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.B. Chung, J. B. Kuo
2005ISCASEnergy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications.G. Y. Liu, N. C. Wang, J. B. Kuo
2002ISCAS0.8 V CMOS content-addressable-memory (CAM) cell circuit with a fast tag-compare capability using bulk PMOS dynamic-threshold (BP-DTMOS) technique based on standard CMOS technology for low-voltage VLSI systems.E. Shen, J. B. Kuo