Jae Cheol Son
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
1995–2018
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCAS | Contention-Free High-Speed Clock-Gate based on Set/Reset Latch for Wide Voltage Scaling. | Min-Su Kim, Ah-Reum Kim, Yong-geol Kim, Chunghee Kim, Dong-Yeop Kim, Jong-Woo Kim, Daeseong Lee, Hyun Lee, Jungyul Pyo, Youngmin Shin, Jae Cheol Son |
| 1995 | ASPDAC | Architectural simulation for a programmable DSP chip set. | Jong Tae Lee, Jaemin Kim, Jae Cheol Son |