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James B. Kuo

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

1

Active years

1993–2014

Best venue rank

C

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2014ISCASCritical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs.Gregory J. Y. Lin, Chienbo B. Hsu, James B. Kuo
2010ISCASLow-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.Chih-Hsiang Lin, James B. Kuo
2003ISCASNovel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI.P. C. Chen, James B. Kuo
2000ISCASA novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability.Bo-Ting Wang, James B. Kuo
1994ISCASA Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSI.James B. Kuo, B. Y. Chen, Mark W. Mao
1994ISCASA BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit.James B. Kuo, K. W. Su, J. H. Lou
1993ISCASA BiCMOS Dynamic Divider Circuit Using a Restoring Iterative Architecture with Carry Look Ahead for CPU VLSI.James B. Kuo, Hung-Pin Chen, H. J. Huang
1993ISCASA Coded Block Neural Network System Suitable for VLSI Implementation Using an Adaptive Learning-rate Epoch-based Back Propagation Technique.Mark W. Mao, B. Y. Chen, James B. Kuo