| 2023 | ACSSC | Parallelization of the Shift and Add Reducer. | Ryan Swann, James E. Stine |
| 2023 | ACSSC | Design Exploration of Magnitude Comparators for RISC-V System-on-Chip Architectures. | Alexander Underwood, James E. Stine |
| 2022 | ARITH | Point-Targeted Sparseness and Ling Transforms on Parallel Prefix Adder Trees. | Teodor-Dumitru Ene, James E. Stine |
| 2022 | ISCAS | Implementation of High Performance IEEE 754-Posit Conversion Hardware. | Brett Mathis, James E. Stine |
| 2021 | ACSSC | A Reconfigurable Architecture for Improvement and Optimization of Advanced Encryption Standard Hardware. | Ryan Swann, James E. Stine |
| 2021 | ICCD | A Comprehensive Exploration of the Parallel Prefix Adder Tree Space. | Teodor-Dumitru Ene, James E. Stine |
| 2020 | ACSSC | An Architecture for Improving Variable Radix Real and Complex Division Using Recurrence Division. | James E. Stine, Milos D. Ercegovac, Jean-Michel Muller |
| 2020 | ICCD | A Novel Rounding Algorithm for a High Performance IEEE 754 Double-Precision Floating-Point Multiplier. | S. Ross Thompson, James E. Stine |
| 2019 | ACSSC | Conditional Estimation of Residuals with Prescaling for Use in Low-Energy Division Units. | Milos D. Ercegovac, James E. Stine |
| 2019 | ISCAS | Fast and Area-Efficient SRAM Word-Line Optimization. | Bin Wu, James E. Stine, Matthew R. Guthaus |
| 2019 | WCAE | An Emphasis on Memory and Processor Interactions in Undergraduate Computer Architecture Education. | Alexander Underwood, James E. Stine |
| 2018 | ACSSC | Low-Area Memoryless optimized Soft-Decision Viterbi Decoder with Dedicated Paralell Squaring Architecture. | John D. Tobola, James E. Stine |
| 2017 | ACSSC | A combined IEEE half and single precision floating point multipliers for deep learning. | Tuan D. Nguyen, James E. Stine |
| 2016 | ACSSC | Optimized multipartite table methods for elementary function computation. | James E. Stine, Masoud Sadeghian |
| 2016 | ICCAD | OpenRAM: an open-source memory compiler. | Matthew R. Guthaus, James E. Stine, Samira Ataei, Brian Chen, Bin Wu, Mehedi Sarwar |
| 2016 | ICCD | A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. | Samira Ataei, James E. Stine, Matthew R. Guthaus |
| 2014 | ISCAS | Additional optimizations for parallel squarer units. | Son Bui, James E. Stine |
| 2014 | ISCAS | Optimized cubic chebyshev interpolator for elementary function hardware implementations. | Masoud Sadeghian, James E. Stine, E. George Walters III |
| 2014 | ISCAS | Enhancing the Unified Logical Effort algorithm for branching and load distribution. | Mehedi Sarwar, James E. Stine |
| 2012 | ACSSC | Optimized low-power elementary function approximation for Chebyshev series approximations. | Masoud Sadeghian, James E. Stine |
| 2012 | ACSSC | Session TA6b: Low power II (invited). | James E. Stine |
| 2011 | ISCAS | A recursive-divide architecture for multiplication and division. | James E. Stine, Amey Phadke, Surpriya Tike |
| 2008 | ACSSC | Single-ended half-swing low-power SRAM design. | Harsha Choday, James E. Stine |
| 2008 | ACSSC | Session WA5b: Low power methods. | James E. Stine |
| 2006 | ISCAS | Low power binary addition using carry increment adders. | Johannes Grad, James E. Stine |
| 2006 | ISCAS | Compressed symmetric tables for accurate function approximation of reciprocals. | James E. Stine, Nitin Naresh |
| 2005 | ISCAS | Constant addition utilizing flagged prefix structures. | James E. Stine, Christopher R. Babb, Vibhuti B. Dave |
| 2005 | ISCAS | A combined two's complement and floating-point comparator. | James E. Stine, Michael J. Schulte |
| 2003 | DSD | Variations on Truncated Multiplication. | James E. Stine, Oliver M. Duverne |
| 2001 | ICCD | Combined IEEE Compliant and Truncated Floating Point Multipliers for Reduced Power Dissipation. | Kent E. Wires, Michael J. Schulte, James E. Stine |
| 1997 | ARITH | Symmetric Bipartite Tables for Accurate Function Approximation. | Michael J. Schulte, James E. Stine |