Jan Lappas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
2019–2025
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DDECS | Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables. | Hussien Abdo, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn |
| 2024 | ASPDAC | Timing Analysis beyond Complementary CMOS Logic Styles. | Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn, Sani R. Nassif |
| 2022 | DATE | Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node. | Jan Lappas, Andr Lucas Chinazzo, Christian Weis, Chenyang Xia, Zhihang Wu, Leibin Ni, Norbert Wehn |
| 2022 | ETS | Machine learning based soft error rate estimation of pass transistor logic in high-speed communication. | Zhe Zhang, Jan Lappas, Andr Lucas Chinazzo, Christian Weis, Zhihang Wu, Leibin Ni, Norbert Wehn, Mehdi B. Tahoori |
| 2019 | ISCAS | An In-DRAM Neural Network Processing Engine. | Chirag Sudarshan, Jan Lappas, Muhammad Mohsin Ghaffar, Vladimir Rybalkin, Christian Weis, Matthias Jung, Norbert Wehn |