Jan Schier
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2003–2004
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | FPL | Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. | Jan Schier, Antonin Hermanek |
| 2003 | FPL | MATLAB/Simulink Based Methodology for Rapid-FPGA-Prototyping. | Miroslav Lcko, Jan Schier, Milan Tich, Markus Khl |