Jaroslav Skarvada
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2006–2010
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | DDECS | Reduction of power dissipation through parallel optimization of test vector and scan register sequences. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2010 | DSD | The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. | Zdenek Kotsek, Jaroslav Skarvada, Josef Strnadel |
| 2008 | DSD | Power Conscious RTL Test Scheduling. | Jaroslav Skarvada, Zdenek Kotsek, Tomas Herrman |
| 2007 | DSD | Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. | Jaroslav Skarvada, Tomas Herrman, Zdenek Kotsek |
| 2006 | DDECS | Test Scheduling for SoC under Power Constraints. | Jaroslav Skarvada |