Jay J. Nejedlo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2003–2009
Best venue rank
A
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ITC | Intel | Jay J. Nejedlo, Rahul Khanna |
| 2004 | ITC | Functional Test Coverage Effectiveness on the Decline. | Jay J. Nejedlo |
| 2003 | ITC | TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms. | Jay J. Nejedlo |
| 2003 | ITC | IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO. | Jay J. Nejedlo |