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Jean Blanger

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

6

Venues

2

Active years

2012–2015

Best venue rank

C

Where they publish

Papers

6 indexed papers, newest first.

YearVenueTitleAuthors
2015IECONFPGA-based real-time simulation of a PSIM model: An indirect matrix converter case study.Tarek Ould Bachir, Asma Merdassi, Sbastien Cense, Handy Fortin-Blanchette, Jean Blanger
2014IECONReal-time simulation of modular multilevel converter on FPGA with sub-microsecond time-step.Luc-Andr Grgoire, Handy Fortin-Blanchette, Kamal Al-Haddad, Wei Li, Jean Blanger
2013IECONValidation of eHS FPGA reconfigurable low-latency electric and power electronic circuit solver.Jean Blanger, Amine Yamane, Andy Yen, Sbastien Cense, Pierre-Yves Robert
2013IECONReal-time and faster-than-real-time simulation of Modular Multilevel Converters using standard multi-core CPU and FPGA chips.Can Wang, Wei Li, Jean Blanger
2012IECONGeneral-purpose reconfigurable low-latency electric circuit and motor drive solver on FPGA.Christian Dufour, Sbastien Cense, Tarek Ould-Bachir, Luc-Andr Grgoire, Jean Blanger
2012SCReal-Time Simulation Using Transient Stability, ElectroMagnetic Transient and FPGA-Based High-Resolution Solvers.Christian Dufour, Vahid Jalili-Marandi, Jean Blanger