| 2017 | DATE | Structural design optimization for deep convolutional neural networks using stochastic computing. | Zhe Li, Ao Ren, Ji Li, Qinru Qiu, Bo Yuan, Jeffrey Draper, Yanzhi Wang |
| 2017 | IJCNN | Hardware-driven nonlinear activation for stochastic computing based deep convolutional neural networks. | Ji Li, Zihao Yuan, Zhe Li, Caiwen Ding, Ao Ren, Qinru Qiu, Jeffrey Draper, Yanzhi Wang |
| 2016 | DAC | Accelerating soft-error-rate (SER) estimation in the presence of single event transients. | Ji Li, Jeffrey Draper |
| 2016 | FPGA | SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. | Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper |
| 2014 | ISCAS | Optimal techniques for assigning inter-tier signals to 3D-vias with path control in a 3DIC. | Neela Gopi, Jeffrey Draper |
| 2013 | ISCAS | Logic-on-logic partitioning techniques for 3-dimensional integrated circuits. | Neela Gopi, Jeffrey Draper |
| 2013 | SC | Leakage energy estimates for HPC applications. | Aditya M. Deshpande, Jeffrey Draper |
| 2000 | ISCAS | A Zener-diode-activated ESD protection circuit for sub-micron CMOS processes. | Louis Luh, John Choma Jr., Jeffrey Draper |
| 2000 | ISCAS | Performance optimization for high-order continuous-time ΣΔ modulators with extra loop delay. | Louis Luh, John Choma Jr., Jeffrey Draper |