Jeonghyu Yang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2025–2025
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ASPDAC | A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. | Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han |
| 2025 | ISCAS | A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees. | Yooseong Jang, Seokmin Yun, Jeonghyu Yang, Taeho Shin, Eunji Song, Jaeduk Han |
| 2025 | ISCAS | A 96-Gb/s PAM-8 Transmitter with Transition-Boosted Current-Mode Logic Driver in 40-nm CMOS for Wireline Communication. | Bona Lim, Hanhee Jo, Heedo Jeong, Jeonghyu Yang, Jaeduk Han |