A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology.
Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han
Browse the full ASPDAC paper archive.
Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han
Browse the full ASPDAC paper archive.