Jiangmin Gu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
2002–2005
Best venue rank
C
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ISCAS | An area efficient 64-bit square root carry-select adder for low power applications. | Yajuan He, Chip-Hong Chang, Jiangmin Gu |
| 2005 | ISCAS | A novel covalent redundant binary Booth encoder. | Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy |
| 2003 | ICASSP | Low voltage, low power (5: 2) compressor cell for fast arithmetic circuits. | Jiangmin Gu, Chip-Hong Chang |
| 2003 | ISCAS | Ultra low voltage, low power 4-2 compressor for high speed multiplications. | Jiangmin Gu, Chip-Hong Chang |
| 2003 | ISCAS | A novel hybrid pass logic with static CMOS output drive full-adder cell. | Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang |
| 2002 | ISCAS | An interconnect optimized floorplanning of a scalar product macrocell. | Jiangmin Gu, Chip-Hong Chang, Kiat Seng Yeo |