| 2026 | DATE | Hetero-ChipletSim: Bridging Chiplet, Interconnect and Packaging Heterogeneity in Multi-Chiplet System Simulation. | Xuguang Yuan, Jiangyuan Gu, Qidie Wu, Yang Hu, Shaojun Wei, Shouyi Yin |
| 2025 | ASPDAC | DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures. | Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin |
| 2025 | ICCAD | P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture. | Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin |
| 2023 | DAC | RMP-MEM: A HW/SW Reconfigurable Multi-Port Memory Architecture for Multi-PEA Oriented CGRA. | Qidie Wu, Jiangyuan Gu, Youxu Lin, Boxiao Han, Hongjun He, Yang Hu, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2022 | DAC | Mixed-granularity parallel coarse-grained reconfigurable architecture. | Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin |
| 2022 | DAC | GEML: GNN-based efficient mapping method for large loop applications on CGRA. | Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao |
| 2021 | ASPDAC | Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs. | Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2021 | ASPDAC | A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating. | Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2020 | DAC | TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. | Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin |
| 2017 | ASPDAC | Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. | Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei |
| 2017 | DAC | Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. | Jiangyuan Gu, Shouyi Yin, Shaojun Wei |