| 2026 | ASPDAC | Timing-Aware Optimization of Die-Level Routing and TDM Assignment for Multi-FPGA Systems. | Yijun Chen, Haoyuan Li, Chunyan Pei, Jianwang Zhai, Kang Zhao, Wenjian Yu |
| 2026 | ASPDAC | HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis. | Zibo Hu, Zhe Lin, Renjing Hou, Xingyu Qin, Jianwang Zhai, Kang Zhao |
| 2026 | DATE | MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA. | Zhenghao Chen, Yuan Pu, Hairuo Han, Yuntao Nie, Jiajun Qin, Yuhan Qin, Tairu Qiu, Zhuolun He, Jianwang Zhai, Bei Yu, Kang Zhao |
| 2026 | DATE | DynaOpt: A Heterogeneous Logic Optimization Framework with Dynamic Sequence Generation. | Xingyu Qin, Guande Dong, Jianwang Zhai, Kang Zhao |
| 2026 | DATE | AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs. | Yingxin Zeng, Binghao Cheng, Jianwang Zhai, Kang Zhao, Zhe Lin |
| 2026 | ISCAS | Performance Pragma-Based Design Space Pruning and Exploration for High-Level Synthesis. | Donghao Guo, Zhe Lin, Jianwang Zhai, Kang Zhao |
| 2025 | ASPDAC | The Survey of 2.5D Integrated Architecture: An EDA perspective. | Shixin Chen, Hengyuan Zhang, Zichao Ling, Jianwang Zhai, Bei Yu |
| 2025 | ASPDAC | PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis. | Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao |
| 2025 | ASPDAC | FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs. | Zirui Li, Kanglin Tian, Jianwang Zhai, Zixuan Li, Shixiong Kai, Siyuan Xu, Bei Yu, Kang Zhao |
| 2025 | DAC | IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction. | Feng Guo, Yueyue Xi, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Chuan Shi |
| 2025 | DAC | HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design. | Xinya Luan, Zhe Lin, Kai Shi, Jianwang Zhai, Kang Zhao |
| 2025 | DAC | VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration. | Kai Shi, Zhe Lin, Xinya Luan, Jianwang Zhai, Kang Zhao |
| 2025 | DAC | Truly Pre-Routing Timing Prediction via Considering Power Delivery Network. | Yuyang Ye, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang, Longxing Shi |
| 2025 | DATE | IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning. | Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi |
| 2025 | DATE | WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction. | Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi |
| 2025 | ICCAD | Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits. | Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu |
| 2025 | ISCAS | HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules. | Zixuan Li, Kanglin Tian, Jianwang Zhai, Zirui Li, Kang Zhao |
| 2024 | AAAI | Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. | Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong |
| 2024 | DATE | Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model. | Jingyu Jia, Jianwang Zhai, Kang Zhao |
| 2024 | ICCAD | PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network. | Jiawei Liu, Jianwang Zhai, Mingyu Zhao, Zhe Lin, Bei Yu, Chuan Shi |
| 2024 | ISCAS | Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing. | Zirui Li, Jianwang Zhai, Zixuan Li, Zhongdong Qi, Kang Zhao |
| 2023 | ASPDAC | Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning. | Jianwang Zhai, Yici Cai, Bei Yu |
| 2021 | ICCAD | BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. | Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong |
| 2021 | ICCAD | McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. | Jianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou, Bei Yu |