| 2026 | ASPDAC | Formalization of Rectification Learning for Economic Design Updates. | Victor N. Kravets, Jie-Hong R. Jiang |
| 2026 | SAT | Exact Symbolic Reasoning for Nonlinear Stochastic SMT via Cylindrical Algebraic Decomposition. | Jung-Cheng Lin, Chia-Hsuan Su, Jie-Hong R. Jiang, Hiroshi Unno |
| 2026 | TACAS | Error-Tolerant Quantum State Discrimination: Optimization and Quantum Circuit Synthesis. | Chien-Kai Ma, Bo-Hung Chen, Tian-Fu Chen, Dah-Wei Chiou, Jie-Hong R. Jiang |
| 2025 | ICCAD | Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization. | Jiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko |
| 2025 | ICCAD | GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing. | Hsin-Ying Tsai, Chung-Kai Wu, Chih-Cheng Hsu, Jie-Hong R. Jiang |
| 2025 | QCE | A Measure-and-Prepare Framework for Arbitrary Quantum Gate Excision and its Applications. | Tian-Fu Chen, Yu-Hung Pan, Ting-Hsun Chi, Po-Hung Chen, Dah-Wei Chiou, Jie-Hong R. Jiang |
| 2025 | QCE | Optimal Qubit Reuse for Quantum Computation with Gate Reordering and Eager Measurement. | Wen-Chen Yu, Tian-Fu Chen, Yu-Hsiang Chan, Jie-Hong R. Jiang, Dah-Wei Chiou, Yao-Wen Chang |
| 2025 | TACAS | SliQSim: A Quantum Circuit Simulator and Solver for Probability and Statistics Queries. | Tian-Fu Chen, Jie-Hong R. Jiang |
| 2024 | AAAI | Unifying Decision and Function Queries in Stochastic Boolean Satisfiability. | Yu-Wei Fan, Jie-Hong R. Jiang |
| 2024 | IJCAI | Knowledge Compilation for Incremental and Checkable Stochastic Boolean Satisfiability. | Che Cheng, Yun-Rong Luo, Jie-Hong R. Jiang |
| 2024 | QCE | A Holistic Approach to Rotation Synthesis for Fault- Tolerant Quantum Computation. | Tian-Fu Chen, Cheng-Han Liu, Jie-Hong R. Jiang |
| 2023 | AAAI | Lifting (D)QBF Preprocessing and Solving Techniques to (D)SSAT. | Che Cheng, Jie-Hong R. Jiang |
| 2023 | AAAI | SharpSSAT: A Witness-Generating Stochastic Boolean Satisfiability Solver. | Yu-Wei Fan, Jie-Hong R. Jiang |
| 2023 | AAAI | Second-Order Quantified Boolean Logic. | Jie-Hong R. Jiang |
| 2023 | DAC | Don't-Care Aware ESOP Extraction via Reduced Decomposition-Tree Exploration. | Chun-Yu Wei, Jie-Hong R. Jiang |
| 2023 | ICCAD | WolFEx: Word-Level Function Extraction and Simplification from Gate-Level Arithmetic Circuits. | Kuo-Wei Ho, Shao-Ting Chung, Tian-Fu Chen, Yu-Wei Fan, Che Cheng, Cheng-Han Liu, Jie-Hong R. Jiang |
| 2023 | QCE | VanQiRA: A Vanishing-State-Based Framework for Quantum Circuit Runtime Assertion. | Tian-Fu Chen, Chun-Yu Wei, Jie-Hong R. Jiang |
| 2022 | DAC | Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification. | Chun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang |
| 2022 | ICCAD | Language Equation Solving via Boolean Automata Manipulation. | Wan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang |
| 2022 | IJCAI | Encoding Probabilistic Graphical Models into Stochastic Boolean Satisfiability. | Cheng-Han Hsieh, Jie-Hong R. Jiang |
| 2022 | QCE | Partial Equivalence Checking of Quantum Circuits. | Tian-Fu Chen, Jie-Hong R. Jiang, Min-Hsiu Hsieh |
| 2021 | AAAI | A Sharp Leap from Quantified Boolean Formula to Stochastic Boolean Satisfiability Solving. | Pei-Wei Chen, Yu-Ching Huang, Jie-Hong R. Jiang |
| 2021 | AAAI | Dependency Stochastic Boolean Satisfiability: A Logical Formalism for NEXPTIME Decision Problems with Uncertainty. | Nian-Ze Lee, Jie-Hong R. Jiang |
| 2021 | DAC | Bit-Slicing the Hilbert Space: Scaling Up Accurate Quantum Circuit Simulation. | Yuan-Hung Tsai, Jie-Hong R. Jiang, Chiao-Shan Jhang |
| 2021 | DAC | Deep Integration of Circuit Simulator and SAT Solver. | He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amar, Alan Mishchenko, Robert K. Brayton |
| 2021 | DATE | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. | Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jnata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee |
| 2021 | ICCAD | A Circuit-Based SAT Solver for Logic Synthesis. | He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko |
| 2020 | DAC | Time Multiplexing via Circuit Folding. | Po-Chun Chien, Jie-Hong R. Jiang |
| 2020 | DAC | SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. | He-Teng Zhang, Jie-Hong R. Jiang |
| 2020 | DATE | Engineering Change Order for Combinational and Sequential Design Rectification. | Jie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee |
| 2020 | DATE | Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development Cycle. | Victor N. Kravets, Jie-Hong R. Jiang, Heinz Riener |
| 2020 | ICCAD | Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. | Yu-Chou Lin, Jie-Hong R. Jiang |
| 2020 | ICCAD | Symbolic Uniform Sampling with XOR Circuits. | Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets |
| 2019 | ASPDAC | An approximation algorithm to the optimal switch control of reconfigurable battery packs. | Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang |
| 2019 | CP | A Cube Distribution Approach to QBF Solving and Certificate Minimization. | Li-Cheng Chen, Jie-Hong R. Jiang |
| 2019 | DAC | Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. | Hao Chen, Shao-Chun Hung, Jie-Hong R. Jiang |
| 2019 | DAC | Comprehensive Search for ECO Rectification Using Symbolic Sampling. | Victor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang |
| 2019 | ICCAD | Time-Frame Folding: Back to the Sequentiality. | Po-Chun Chien, Jie-Hong R. Jiang |
| 2019 | ICCAD | Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. | Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang |
| 2018 | DAC | Efficient computation of ECO patch functions. | Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton |
| 2018 | DAC | Cost-aware patch generation for multi-target function rectification of engineering change orders. | He-Teng Zhang, Jie-Hong R. Jiang |
| 2018 | ICCAD | Logic synthesis of binarized neural networks for efficient circuit implementation. | Chia-Chih Chi, Jie-Hong R. Jiang |
| 2018 | ICCAD | Canonicalization of threshold logic representation and its applications. | Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang |
| 2018 | IJCAI | Solving Exist-Random Quantified Stochastic Boolean Satisfiability via Clause Selection. | Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang |
| 2017 | DAC | Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation. | Chun-Ning Lai, Jie-Hong R. Jiang |
| 2017 | DAC | Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits. | Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang |
| 2017 | ICCAD | Sequential engineering change order under retiming and resynthesis. | Nian-Ze Lee, Victor N. Kravets, Jie-Hong R. Jiang |
| 2017 | IJCAI | Solving Stochastic Boolean Satisfiability under Random-Exist Quantification. | Nian-Ze Lee, Yen-Shi Wang, Jie-Hong R. Jiang |
| 2016 | CAV | String Analysis via Automata Manipulation with Logic Circuit Representation. | Hung-En Wang, Tzung-Lin Tsai, Chun-Han Lin, Fang Yu, Jie-Hong R. Jiang |
| 2016 | DAC | Design partitioning for large-scale equivalence checking and functional correction. | Grace Wu, Yi-Tin Sun, Jie-Hong R. Jiang |
| 2016 | ICCAD | Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. | Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang |
| 2015 | DAC | Scalable sequence-constrained retention register minimization in power gating design. | Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang |
| 2015 | ICCAD | Property-Directed Synthesis of Reactive Systems from Safety Specifications. | Ting-Wei Chiang, Jie-Hong R. Jiang |
| 2015 | ICCAD | A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. | Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang |
| 2015 | SAT | QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving. | Kuan-Hua Tu, Tzu-Chien Hsu, Jie-Hong R. Jiang |
| 2014 | DAC | Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. | Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang |
| 2014 | DAC | Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. | Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang |
| 2014 | ICCAD | Towards formal evaluation and verification of probabilistic design. | Nian-Ze Lee, Jie-Hong R. Jiang |
| 2014 | SAT | QBF Resolution Systems and Their Proof Complexities. | Valeriy Balabanov, Magdalena Widl, Jie-Hong R. Jiang |
| 2013 | DAC | Synthesis of feedback decoders for initialized encoders. | Kuan-Hua Tu, Jie-Hong R. Jiang |
| 2013 | ICCAD | Automatic test pattern generation for delay defects using timed characteristic functions. | Shin-Yann Ho, Shuo-Ren Lin, Ko-Lung Yuan, Chien-Yen Kuo, Kuan-Yu Liao, Jie-Hong R. Jiang, Chien-Mo James Li |
| 2013 | ICCAD | Encoding multi-valued functions for symmetry. | Ko-Lung Yuan, Chien-Yen Kuo, Jie-Hong R. Jiang, Meng-Yen Li |
| 2012 | ASPDAC | Clock rescheduling for timing engineering change orders. | Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang |
| 2012 | ICCAD | Compiling program control flows into biochemical reactions. | De-An Huang, Jie-Hong R. Jiang, Ruei-Yang Huang, Chi-Yun Cheng |
| 2011 | CAV | Resolution Proofs and Skolem Functions in QBF Evaluation and Applications. | Valeriy Balabanov, Jie-Hong R. Jiang |
| 2011 | ICCAD | Towards completely automatic decoder synthesis. | Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang |
| 2010 | ASPDAC | TRECO: dynamic technology remapping for timing engineering change orders. | Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang |
| 2010 | DAC | BooM: a decision procedure for boolean matching with abstraction and dynamic learning. | Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang |
| 2010 | ICCAD | Boolean matching of function vectors with strengthened learning. | Chih-Fan Lai, Jie-Hong R. Jiang, Kuo-Hua Wang |
| 2009 | CAV | Quantifier Elimination via Functional Composition. | Jie-Hong R. Jiang |
| 1997 | ASPDAC | BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. | Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei |