| 2026 | AAAI | Model Counting for Dependency Quantified Boolean Formulas. | Long-Hin Fung, Che Cheng, Jie-Hong Roland Jiang, Friedrich Slivovsky, Tony Tan |
| 2025 | AAAI | Solving Higher-Order Quantified Boolean Satisfiability via Higher-Order Model Checking. | Hiroshi Unno, Takeshi Tsukada, Jie-Hong Roland Jiang |
| 2025 | FMCAD | Unifying DQMax#SAT and DSSAT: Polynomial-Time Reduction and Applications. | Ilo Chen, Che Cheng, Jie-Hong Roland Jiang |
| 2025 | SAT | Fine-Grained Complexity Analysis of Dependency Quantified Boolean Formulas. | Che Cheng, Long-Hin Fung, Jie-Hong Roland Jiang, Friedrich Slivovsky, Tony Tan |
| 2024 | DAC | Boolean Matching Reversible Circuits: Algorithm and Complexity. | Tian-Fu Chen, Jie-Hong Roland Jiang |
| 2024 | FMCAD | 2-DQBF Solving and Certification via Property-Directed Reachability Analysis. | Long-Hin Fung, Che Cheng, Yu-Wei Fan, Tony Tan, Jie-Hong Roland Jiang |
| 2024 | ICCAD | Accelerating Quantum Circuit Simulation with Symbolic Execution and Loop Summarization. | Tian-Fu Chen, Yu-Fang Chen, Jie-Hong Roland Jiang, Sra Jobranov, Ondrej Lengl |
| 2022 | SAT | Quantifier Elimination in Stochastic Boolean Satisfiability. | Hao-Ren Wang, Kuan-Hua Tu, Jie-Hong Roland Jiang, Christoph Scholl |
| 2021 | ICCAD | Compatible Equivalence Checking of X-Valued Circuits. | Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang Ric Huang |
| 2020 | DAC | Circuit Learning for Logic Regression on High Dimensional Boolean Space. | Pei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong Roland Jiang |
| 2019 | AAAI | A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving. | Christoph Scholl, Jie-Hong Roland Jiang, Ralf Wimmer, Aile Ge-Ernst |
| 2018 | DAC | Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. | Run-Yi Wang, Chia-Cheng Pai, Junjie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang |
| 2018 | ICSE | Static detection of API call vulnerabilities in iOS executables. | Chun-Han Lin, Fang Yu, Jie-Hong Roland Jiang, Tevfik Bultan |
| 2016 | AAAI | Clauses Versus Gates in CEGAR-Based 2QBF Solving. | Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl |
| 2016 | SAT | 2QBF: Challenges and Solutions. | Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton |
| 2015 | AAAI | Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs. | Valeriy Balabanov, Jie-Hong Roland Jiang, Mikolas Janota, Magdalena Widl |
| 2015 | ICCAD | Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. | Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang |
| 2015 | ICCAD | SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. | Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang |
| 2013 | FMCAD | Synthesizing multiple boolean functions using interpolation on a single proof. | Georg Hofferek, Ashutosh Gupta, Bettina Knighofer, Jie-Hong Roland Jiang, Roderick Bloem |
| 2012 | CAV | When Boolean Satisfiability Meets Gaussian Elimination in a Simplex Way. | Cheng-Shen Han, Jie-Hong Roland Jiang |
| 2012 | DAC | Functional timing analysis made fast and general. | Yi-Ting Chung, Jie-Hong Roland Jiang |
| 2012 | MEMOCODE | Improving design verifiability by early RTL coverability analysis. | Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu |
| 2012 | SAT | Henkin Quantifiers and Boolean Formulae. | Valeriy Balabanov, Hui-Ju Katherine Chiang, Jie-Hong Roland Jiang |
| 2010 | ICCAD | A robust functional ECO engine by SAT proof minimization and interpolation techniques. | Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang |
| 2009 | FPGA | Scalable don't-care-based logic optimization and resynthesis. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang |
| 2009 | ICCAD | Interpolating functions from large Boolean relations. | Jie-Hong Roland Jiang, Hsuan-Po Lin, Wei-Lun Hung |
| 2008 | DAC | Bi-decomposing large Boolean functions via interpolation and satisfiability solving. | Ruei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung |
| 2008 | ICCAD | To SAT or not to SAT: Ashenhurst decomposition in a large scale. | Hsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee |
| 2008 | ICCD | A dynamic accuracy-refinement approach to timing-driven technology mapping. | Sz-Cheng Huang, Jie-Hong Roland Jiang |
| 2007 | ICCAD | Inductive equivalence checking under retiming and resynthesis. | Jie-Hong Roland Jiang, Wei-Lun Hung |
| 2007 | ICCAD | Scalable exploration of functional dependency by interpolation and incremental SAT solving. | Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko |
| 2005 | DATE | Efficient Solution of Language Equations Using Partitioned Representations. | Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko |
| 2005 | TACAS | On Some Transformation Invariants Under Retiming and Resynthesis. | Jie-Hong Roland Jiang |
| 2004 | CAV | Functional Dependency for Verification Reduction. | Jie-Hong Roland Jiang, Robert K. Brayton |
| 2004 | ICCAD | On breakable cyclic definitions. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 2003 | DATE | Reducing Multi-Valued Algebraic Operations to Binary. | Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton |
| 1999 | ICCAD | Optimum loading dispersion for high-speed tree-type decision circuitry. | Jie-Hong Roland Jiang, Iris Hui-Ru Jiang |
| 1998 | DAC | Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. | Jie-Hong Roland Jiang, Jing-Yang Jou, Juinn-Dar Huang |