| 2023 | ASPDAC | On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. | Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2023 | ISCAS | A Digital Jitter Compensation Technique for Analog-to-Digital Converters. | Ding-Hao Wang, Jieh-Tsorng Wu |
| 2016 | ISCAS | A computationally-efficient PWM technique for digital class-D amplifiers. | Chih-Min Chang, Jieh-Tsorng Wu |
| 2013 | ISCAS | A 1-V 100-dB dynamic range 24.4-kHz bandwidth delta-sigma modulator. | Chia-Ling Chang, Jieh-Tsorng Wu |
| 2012 | ISCAS | A 10-Bit 200-MS/s digitally-calibrated pipelined ADC using switching opamps. | Bing-Nan Fang, Jieh-Tsorng Wu |
| 2005 | ISCAS | A robust background calibration technique for switched-capacitor pipelined ADCs. | Jen-Lin Fan, Jieh-Tsorng Wu |
| 2004 | ISCAS | Multi-level memory systems using error control codes. | Hsie-Chia Chang, Chien-Ching Lin, Tien-Yuan Hsiao, Jieh-Tsorng Wu, Ta-Hui Wang |
| 2004 | ISCAS | A statistical background calibration technique for flash analog-to-digital converters. | Chun-Cheng Huang, Jieh-Tsorng Wu |
| 2003 | ISCAS | A digital background calibration technique for pipelined analog-to-digital converters. | Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu |
| 2001 | ISCAS | Highly linear 100 MHz CMOS programmable gain amplifiers. | Cheng-Chung Hsu, Jieh-Tsorng Wu |