Jielun Tan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2019–2021
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | SIGCSE | RISC-V Reward: Building Out-of-Order Processors in a Computer Architecture Design Course with an Open-Source ISA. | Stephen A. Zekany, Jielun Tan, James A. Connelly, Ronald G. Dreslinski |
| 2021 | WCAE | Teaching Out-of-Order Processor Design with the RISC-V ISA. | Stephen A. Zekany, Jielun Tan, James A. Connolly |
| 2020 | DAC | R2D3: A Reliability Engine for 3D Parallel Systems. | Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski |
| 2019 | ISLPED | 3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology. | Aporva Amarnath, Javad Bagherzadeh, Jielun Tan, Ronald G. Dreslinski |