Jin-Fa Lin
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2006–2018
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCAS | An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme. | Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu |
| 2012 | ISCAS | Low power 10-transistor full adder design based on degenerate pass transistor logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu |
| 2006 | ISCAS | A high speed and energy efficient full adder design using complementary & level restoring carry logic. | Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho |