Jingcheng Gu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2025–2026
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | An Operator-Circuit Co-design Digital SOT-MRAM Computing-in-Memory Accelerator with Double Bit Density and Full-Utilized Bandwidth/Throughput. | Tianshuo Bai, Jingcheng Gu, Lehao Tan, Wente Yi, Haolin Ge, Han Zhang, Zhenyu Xue, He Zhang, Na Lei, Biao Pan |
| 2025 | DATE | HyIMC: Analog-Digital Hybrid In-Memory Computing SoC for High-Quality Low-Latency Speech Enhancement. | Wanru Mao, Hanjie Liu, Guangyao Wang, Tianshuo Bai, Jingcheng Gu, Han Zhang, Xitong Yang, Aifei Zhang, Xiaohang Wei, Meng Wang, Wang Kang |
| 2025 | ICCAD | PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization. | Han Zhang, Zhenyu Xue, Wente Yi, Tianshuo Bai, Lehao Tan, Jingcheng Gu, Weijie Ding, Wang Kang, Biao Pan |