Jinshan Li
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
1
Active years
2025–2026
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | A Sparsity-Aware Reconfigurable Sensing-Quantization Circuit for RRAM-Based Analog Compute-in-Memory. | Zhuoya Chen, Hao Ding, Yunfan Yang, Haisu Zhang, Jinshan Li, Shigeng Zhao, Yunyi Fu, Zongwei Wang, Yimao Cai |
| 2026 | ISCAS | A 1.8-ns, 45fJ/bit Time-Domain Sensing Scheme with Offset-Cancelled Resistance-to-Time Converter and 10 | Shigeng Zhao, Hao Ding, Yunfan Yang, Jinshan Li, Zhuoya Chen, Xing Zhang, Zongwei Wang, Yimao Cai |
| 2025 | ISCAS | SA-CIM: A 28nm 16Mb RRAM-based Sparsity-Aware Compute-In-Memory Macro for Edge AI Algorithm Processing. | Hao Ding, Zongwei Wang, Jinshan Li, Shigeng Zhao, Heting Gao, Junbo Ao, Ling Liang, Yimao Cai, Ru Huang |
| 2025 | ISCAS | HRC-CIM: Hybrid RRAM-Capacitor Cell based Compute-in-Memory with High Linearity, Parallelism and Energy Efficiency. | Jinshan Li, Zongwei Wang, Hao Ding, Yunfan Yang, Shigeng Zhao, Shengyu Bao, Jingwei Sun, Ruiqing Xie, Zhuoya Chen, Yimao Cai, Ru Huang |