Jiong Luo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
16
Venues
7
Active years
2000–2022
Best venue rank
A*
Where they publish
Papers
16 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2022 | DAC | Improving LUT-based optimization for ASICs. | Walter Lau Neto, Luca G. Amar, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon |
| 2021 | DAC | LUT-Based Optimization For ASIC Design Flow. | Luca Gaetano Amar, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2020 | DAC | SAT-Sweeping Enhanced for Logic Synthesis. | Luca G. Amar, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli |
| 2019 | DATE | Scalable Boolean Methods in a Modern Synthesis Flow. | Eleonora Testa, Luca G. Amar, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2018 | DATE | Improvements to boolean resynthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2017 | ASPDAC | Multi-level logic benchmarks: An exactness study. | Luca Gaetano Amar, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli |
| 2017 | DATE | Logic optimization and synthesis: Trends and directions in industry. | Luca Gaetano Amar, Patrick Vuillod, Jiong Luo, Janet Olson |
| 2017 | ICCAD | Enabling exact delay synthesis. | Luca Gaetano Amar, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli |
| 2003 | DATE | Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. | Jiong Luo, Li-Shiuan Peh, Niraj K. Jha |
| 2003 | ICCAD | Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. | Le Yan, Jiong Luo, Niraj K. Jha |
| 2003 | VLSID | Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2002 | HiPC | Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. | Jiong Luo, Niraj K. Jha |
| 2002 | ICCD | Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. | Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha |
| 2002 | VLSID | Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2001 | DAC | Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2000 | ICCAD | Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. | Jiong Luo, Niraj K. Jha |