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Jitesh Poojary

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

3

Active years

2020–2024

Best venue rank

B

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2024ASPDACReinforcing the Connection between Analog Design and EDA (Invited Paper).Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
2024ASPDACAutomated synthesis of mixed-signal ML inference hardware under accuracy constraints.Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar
2022DATEA Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
2022DATEConstructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays.Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2021ASPDACFast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models.Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020DATEGANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020ICCADThe ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2020ICCADA general approach for identifying hierarchical symmetry constraints for analog circuit layout.Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar