Jiteshri Dasari
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
2022–2026
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | VLSID | Universal Formal Verification Approach for Modular Reduction Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2024 | DATE | Combining Formal Verification and Testing for Debugging of Arithmetic Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2023 | DAC | Formal Verification of Restoring Dividers made Fast and Simple. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2023 | ICCAD | Efficient Formal Verification and Debugging of Arithmetic Divider Circuits. | Jiteshri Dasari, Maciej J. Ciesielski |
| 2022 | DDECS | Functional Verification of Arithmetic Circuits: Survey of Formal Methods. | Maciej J. Ciesielski, Atif Yasin, Jiteshri Dasari |