| 2018 | DATE | Symbolic quick error detection using symbolic initial state for pre-silicon verification. | Mohammad Rahmani Fadiheh, Joakim Urdahl, Srinivasa Shashank Nuthakki, Subhasish Mitra, Clark W. Barrett, Dominik Stoffel, Wolfgang Kunz |
| 2017 | VLSID | Dynamic Power Optimization Based on Formal Property Checking of Operations. | Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz |
| 2016 | ICCAD | Properties first? a new design methodology for hardware, and its perspectives in safety analysis. | Joakim Urdahl, Shrinidhi Udupi, Tobias Ludwig, Dominik Stoffel, Wolfgang Kunz |
| 2015 | FDL | Architectural system modeling for correct-by-construction RTL design. | Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz |
| 2012 | DAC | System verification of concurrent RTL modules by compositional path predicate abstraction. | Joakim Urdahl, Dominik Stoffel, Markus Wedler, Wolfgang Kunz |
| 2010 | FMCAD | Path predicate abstraction by complete interval property checking. | Joakim Urdahl, Dominik Stoffel, Jrg Bormann, Markus Wedler, Wolfgang Kunz |