Joe G. Xi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
1993–1996
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1996 | DAC | Useful-Skew Clock Routing With Gate Sizing for Low Power Design. | Joe G. Xi, Wayne Wei-Ming Dai |
| 1996 | ICCAD | Jitter-tolerant clock routing in two-phase synchronous systems. | Joe G. Xi, Wayne Wei-Ming Dai |
| 1995 | DAC | Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution. | Joe G. Xi, Wayne Wei-Ming Dai |
| 1993 | ICCAD | Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models. | Qing Zhu, Wayne Wei-Ming Dai, Joe G. Xi |