John P. Fishburn
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
1983–1999
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1999 | ISCAS | Optimization-based calibration of a static timing analyzer to path delay measurements. | John P. Fishburn |
| 1997 | DATE | Shaping a VLSI wire to minimize Elmore delay. | John P. Fishburn |
| 1995 | ICCAD | Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. | Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn |
| 1992 | DAC | LATTIS: An Iterative Speedup Heuristic for Mapped Logic. | John P. Fishburn |
| 1990 | DAC | A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. | John P. Fishburn |
| 1985 | DAC | Effective use of virtual grid compaction in macro-module generators. | Dwight D. Hill, John P. Fishburn, Mary Diane Palmer Leland |
| 1983 | SIGMOD | Vdd - A VLSI Design Database System. | Kung-Chao Chu, John P. Fishburn, Peter Honeyman, Y. Edmund Lien |