Jooyeon Jeong
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
3
Active years
2022–2026
Best venue rank
A*
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design. | Junghyun Yoon, Jooyeon Jeong, Heechun Park |
| 2024 | DAC | Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. | Jooyeon Jeong, Taewhan Kim |
| 2023 | DATE | Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. | Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim |
| 2022 | ISLPED | Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. | Sehyeon Chung, Jooyeon Jeong, Taewhan Kim |