| 2015 | ASPDAC | Speeding up single pass simulation of PLRUt caches. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2015 | DATE | E-pipeline: elastic hardware/software pipelines on a many-core fabric. | Xi Zhang, Haris Javaid, Muhammad Shafique, Jorgen Peddersen, Jrg Henkel, Sri Parameswaran |
| 2015 | ICCD | Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications. | Jude Angelo Ambrose, Yusuke Yachide, Kapil Batra, Jorgen Peddersen, Sri Parameswaran |
| 2015 | ICCD | RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory. | Su Myat Min Shwe, Kapil Batra, Yusuke Yachide, Jorgen Peddersen, Sri Parameswaran |
| 2014 | ASPDAC | SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs. | Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide |
| 2014 | ASPDAC | A scorchingly fast FPGA-based Precise L1 LRU cache simulator. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2014 | DAC | MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. | Josef Schneider, Jorgen Peddersen, Sri Parameswaran |
| 2012 | VLSID | A Rapid Methodology for Multi-mode Communication Circuit Generation. | Liang Tang, Jorgen Peddersen, Sri Parameswaran |
| 2011 | ICCAD | CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
| 2011 | VLSID | Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
| 2010 | DAC | SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
| 2010 | DATE | Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. | Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran |
| 2010 | NCA | Improved Architectures for Range Encoding in Packet Classification System. | Xin He, Jorgen Peddersen, Sri Parameswaran |
| 2010 | TACAS | ACS: Automatic Converter Synthesis for SoC Bus Protocols. | Karin Avnit, Arcot Sowmya, Jorgen Peddersen |
| 2009 | LCN | LOP_RE: Range encoding for low power packet classification. | Xin He, Jorgen Peddersen, Sri Parameswaran |
| 2007 | ASPDAC | CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. | Jorgen Peddersen, Sri Parameswaran |
| 2007 | VLSID | Energy Driven Application SelfAdaptation. | Jorgen Peddersen, Sri Parameswaran |
| 2005 | VLSID | Rapid Embedded Hardware/Software System Generation. | Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran |