| 2008 | DSD | Logic Transformations by Multiple Wire Network Addition. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | ASPDAC | Functional extension of structural logic optimization techniques. | Jos Alberto Espejo, Luis Entrena, Enrique San Milln, Emilio Olas |
| 2001 | DATE | Generalized reasoning scheme for redundancy addition and removal logic optimization. | Jos Alberto Espejo, Luis Entrena, Enrique San Milln, Emilio Olas |
| 2001 | DSD | On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | ICCAD | On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo |
| 2001 | IOLTS | Logic Optimization of Unidirectional Circuits with Structural Methods. | Luis Entrena, Celia Lpez, Emilio Olas, Enrique San Milln, Jos Alberto Espejo |
| 1999 | DATE | Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. | Enrique San Milln, Luis Entrena, Jos Alberto Espejo, Silvia Chiusano, Fulvio Corno |