Skip to content
cs-conference-ranking.org

Jos Luis Nez-Yez

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

8

Venues

3

Active years

2008–2022

Best venue rank

B

Where they publish

Papers

8 indexed papers, newest first.

YearVenueTitleAuthors
2022DSDEvaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks.Minxuan Kong, Kris Nikov, Jos Luis Nez-Yez
2017FPLA systematic approach to design and optimise streaming applications on FPGA using high-level synthesis.Mohammad Hosseinabady, Jos Luis Nez-Yez
2015FPLEnergy optimization of FPGA-based stream-oriented computing with power gating.Mohammad Hosseinabady, Jos Luis Nez-Yez
2015FPLOptimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices.Mohammad Hosseinabady, Jos Luis Nez-Yez
2014FPLRun-time power gating in hybrid ARM-FPGA devices.Mohammad Hosseinabady, Jos Luis Nez-Yez
2014IJCCINeuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation.Juan Carlos Moctezuma, Jos Luis Nez-Yez, Joseph P. McGeehan
2009FPLA toolset for the analysis and optimization of motion estimation algorithms and processors.Trevor Spiteri, George Vafiadis, Jos Luis Nez-Yez
2008FPLA configurable and programmable motion estimation processor for the H.264 video codec.Jos Luis Nez-Yez, Eddie Hung, Vassilios A. Chouliaras